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JEDEC Solid State Technology Association, 12/01/2013
Publisher: JEDEC
File Format: PDF
$58.00$116.00
Published:01/12/2013
Pages:74
File Size:1 file , 940 KB
Note:This product is unavailable in Russia, Ukraine, Belarus
THERMAL TEST CHIP GUIDELINE (WIRE BOND TYPE CHIP)
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TEST PROCEDURE FOR THE MANAGEMENT OF SINGLE-EVENT EFFECTS IN SEMICONDUCTOR DEVICES FROM HEAVY ION IRRADIATION
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ADDENDUM No. 11 to JESD24 - POWER MOSFET EQUIVALENT SERIES GATE RESISTANCE TEST METHOD
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GUIDE FOR STANDARD PROBE PAD SIZES AND LAYOUTS FOR WAFER LEVEL ELECTRICAL TESTING
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