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  • JEDEC JESD8-15A

JEDEC JESD8-15A

STUB SERIES TERMINATED LOGIC FOR 1.8 V (SSTL_18)

JEDEC Solid State Technology Association, 09/01/2003

Publisher: JEDEC

File Format: PDF

$31.00$62.00


Published:01/09/2003

Pages:21

File Size:1 file , 290 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the SSTL_18 logic switching range, nominally 0 V to 1.8 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages. The VDD value is not specified in this standard; however VDD and VDDQ will have the same voltage level in many cases.

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