JEDEC JESD8-33

.05 Low Voltage Swing Terminated Logic (LVSTL05)

JEDEC Solid State Technology Association, 06/01/2019

Publisher: JEDEC

File Format: PDF

$100.00$201.16

Description

Published:01/06/2019

Pages:10

File Size:1 file , 130 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This standard defines power supply voltage range, dc interface, switching parameter and overshoot/undershoot for high speed low voltage swing terminated NMOS driver family digital circuits. The specifications in this standard represent a minimum set of interface specifications for low voltage terminated circuits. Item 159.03