• Your shopping cart is empty!

  • JEDEC JESD8-8

JEDEC JESD8-8

ADDENDUM No. 8 to JESD8 - STUB SERIES TERMINATED LOGIC FOR 3.3 VOLTS (SSTL_3) A 3.3 V VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS

JEDEC Solid State Technology Association, 08/01/1996

Publisher: JEDEC

File Format: PDF

$29.00$59.00


Published:01/08/1996

Pages:18

File Size:1 file , 1.2 MB

Note:This product is unavailable in Russia, Ukraine, Belarus

This standard is a result of a major effort by the JC-16 Committee to develop a high performance CMOS-based interface suitable for high speed main memory applications in excess of 125 MHz.

More JEDEC standard pdf

JEDEC JESD51-6

JEDEC JESD51-6

INTEGRATED CIRCUIT THERMAL TEST METHOD ENVIRONMENTAL CONDITIONS - FORCED CONVECTION (MOVING AIR)

$24.00 $48.00

JEDEC JESD51-5

JEDEC JESD51-5

EXTENSION OF THERMAL TEST BOARD STANDARDS FOR PACKAGES WITH DIRECT THERMAL ATTACHMENT MECHANISMS

$24.00 $48.00

JEDEC JESD51-7

JEDEC JESD51-7

HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD FOR LEADED SURFACE MOUNT PACKAGES

$26.00 $53.00

JEDEC JEP134

JEDEC JEP134

GUIDELINES FOR PREPARING CUSTOMER-SUPPLIED BACKGROUND INFORMATION RELATING TO A SEMICONDUCTOR-DEVICE FAILURE ANALYSIS

$28.00 $56.00