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  • JEDEC JESD8-8

JEDEC JESD8-8

ADDENDUM No. 8 to JESD8 - STUB SERIES TERMINATED LOGIC FOR 3.3 VOLTS (SSTL_3) A 3.3 V VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS

JEDEC Solid State Technology Association, 08/01/1996

Publisher: JEDEC

File Format: PDF

$29.00$59.00


Published:01/08/1996

Pages:18

File Size:1 file , 1.2 MB

Note:This product is unavailable in Russia, Ukraine, Belarus

This standard is a result of a major effort by the JC-16 Committee to develop a high performance CMOS-based interface suitable for high speed main memory applications in excess of 125 MHz.

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