JEDEC JESD82-16A

DEFINITION OF THE SSTUA32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY TEST FOR DDR2 RDIMM APPLICATIONS

JEDEC Solid State Technology Association, 05/01/2007

Publisher: JEDEC

File Format: PDF

$40.00$80.00

Description

Published:01/05/2007

Pages:43

File Size:1 file , 350 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUA32866 registered buffer with parity test for DDR2 RDIMM applications. The purpose is to provide a standard for the SSTUA32866 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

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