• JEDEC JP001.01

JEDEC JP001.01

FOUNDRY PROCESS QUALIFICATION GUIDELINES (Wafer Fabrication Manufacturing Sites)

JEDEC Solid State Technology Association, 05/01/2004

Publisher: JEDEC

File Format: PDF

$43.00$87.00


Published:01/05/2004

Pages:49

File Size:1 file , 260 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This document provides a guideline for the minimum set of measurements to qualify a new semiconductor wafer process. It is written with particular reference to a generic silicon based CMOS logic technology. While it may be applicable to other technologies (e.g. analog CMOS, bipolar, BICMOS, GaAs, etc.), some sections apply specifically to CMOS. No effort was made in the present document to cover all the qualification requirements for specific other technologies, e.g. Cu/Low K interconnects or ultra thin gate oxide. This publication, is co-sponsored by JEDEC JC-14.2 and the FSA (Fabless Semiconductor Association). It originated at the FSA as a technology specific document, and has evolved into a generic set of qualification requirements.

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